A 100-V LATERAL DMOS TRANSISTOR WITH A 0.3-MICROMETER CHANNEL IN A 1-MICROMETER SILICON-FILM-ON-INSULATOR-ON-SILICON

A new LDMOS transistor structure with break-down voltages above 100 V has been fabricated in silicon-on-insulator-on-silicon (SOIS). This structure has been fabricated by silicon direct bonding (SDB) and etch-back to a typical film thickness of 1-mu-m. The silicon carrier layer (handle) serves as a back-gate electrode, which, under proper bias, improves the transistor characteristics significantly. The effective channel length or basewidth is 0.3-mu-m. Under these conditions, the drift region becomes the current-limiting element. The physics in the drift region in thin silicon films (less-than-or-equal-to 1-mu-m) in the transistor on-state is dominated by the injected electrons from the channel. The limitation of the maximum drain current is given by the quasi-saturation effect. Criteria for the further optimization of SOIS LDMOS transistors are presented.