PLS - A SCHEDULER FOR PIPELINE SYNTHESIS

Pipelining is an effective method to optimize the execution of a loop, especially for digital signal processing (DSP) applications where data enter a circuit regularly. Although throughput and delay are two important optimization criteria, previous work emphasizes mainly on the throughput. We show that the delay time of executing an iteration of a loop has a strong relationship with the cost of the registers and the controller. By minimizing the delay, we could have more silicon area to allocate additional resources which in turn will increase throughput. We iteratively use a forward scheduling and a backward scheduling to achieve this purpose. The algorithm can be used to pipeline a loop with or without loop carried dependencies. Real examples are used to illustrate the proposed method. Experiments on benchmark examples show that the new approach pains a considerable improvement over those by previous approaches.