NAND MODEL FOR FAULT DIAGNOSIS IN COMBINATIONAL LOGIC NETWORKS

被引：45

作者：

HAYES, JP

机构：

来源：

关键词：

D O I：

10.1109/T-C.1971.223162

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

引用

页码：1496 / +

页数：1

共 13 条

ARMSTRONG, DB .

IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS, 1966, EC15 (01) :66-+

[2]

CHANG HY, 1970, FAULT DIAGNOSIS DIGI

[3] AN ALGORITHM FOR NAND DECOMPOSITION UNDER NETWORK CONSTRAINTS [J].

DAVIDSON, ES .

[4]

DIEPHUIS RJ, 1969, THESIS MASS I TECH

[5] FAULT DETECTION IN REDUNDANT CIRCUITS [J].

FRIEDMAN, AD .

IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS, 1967, EC16 (01) :99-+

[6]

GAULT JW, 1969, 13 U IOW THEM PROJ T

[7]

HAYES JP, 1970, R467 U ILL COORD SCI

[8]

KOHAVI I, 1969, 10 P ANN S SWITCH AU, P166

[9]

PAIGE MR, 1969, R414 U ILL COORD SCI

[10]

POAGE JF, 1963, MATHEMATICAL THEORY, P483