Interface properties of MIS structures prepared by plasma oxidation of n-InP

The passivation of InP surfaces has been investigated by growing native thin film oxides with RF plasma oxidation in order to realise high-speed InP metal-insulator-semiconductor field effect transistors (MISFETS). The electrical properties of the InP interface have been analysed by variable-frequency C-V and G-V measurements using the well-established, high-frequency capacitance method, the low-frequency capacitance method and the AC conductance method. In this paper, we report the results obtained for unannealed and postmetallisation-annealed diodes. In addition to the improvement in C-V hyteresis, annealing has the effect of reducing the value of interface state density. Also, it alters the interface electrical properties such as time constant and energy position in the gap. The dispersion of interface state time constant in the depletion region resulting from the potential surface fluctuations has been observed. Also noted is a dispersion of C-V characteristics in the positive bias region. Good correlation has been obtained between theory and the measured conductance curves as a function of frequency at different values of the surface potential. More information about the electrical transport properties of the minority carriers in the weak inversion can be obtained by measuring inversion equivalent parallel conductance G, as a function of temperature. An activation energy of 0.66 eV have been obtained for temperatures above 90 degrees C.