RADIX DIGIT-SERIAL PIPELINED DIVIDER SQUARE-ROOT ARCHITECTURE

The paper presents a new digit-serial architecture for division and square-root which can be pipelined to the bit level to achieve high throughput. The architecture is different from the existing divider/square-root architectures in that is is based on the radix-2'' algorithm. As a result, any type of adder can be used in the proposed digit-serial controlled add/subtract basic cell. The authors present two basic digit-serial controlled add/subtract cells. The first is based on the conventional carry feedback digit-serial adder. The second is based on the carry feed-forward adder, which results in the first reported digit-serial divider/square-root architecture that can be pipelined down to the bit-level. An evaluation of the proposed architecture for different values of the digit size is also presented.