GAAS CAPACITIVELY COUPLED DOMINO LOGIC GATE

被引：5

作者：

HOE, DHK

SALAMA, CAT

机构：

来源：

ELECTRONICS LETTERS | 1989年 / 25卷 / 25期

关键词：

D O I：

10.1049/el:19891146

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：1714 / 1715

页数：2

共 8 条

[1]

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LONG, SI .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (02) :573-580

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[4] CAPACITOR COUPLING OF GAAS DEPLETION-MODE FETS [J].

LIVINGSTONE, AW ;

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[5] CHARGE REDISTRIBUTION AND NOISE MARGINS IN DOMINO CMOS LOGIC [J].

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SHUBAT, AS ;

SALAMA, CAT .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1986, 33 (08) :786-793

[6] HIGH-SPEED INTEGRATED LOGIC WITH GAAS MESFETS [J].

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LIECHTI, CA .

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[7] A HIGH-SPEED DYNAMIC DOMINO CIRCUIT IMPLEMENTED WITH GAAS-MESFETS [J].

YANG, L ;

CHAKHARAPANI, R ;

LONG, SI .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (05) :874-879

[8]

1989, TRINQUINT QED A DESI

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