A PLANARIZATION TECHNOLOGY USING A BIAS-DEPOSITED DIELECTRIC FILM AND AN ETCH-BACK PROCESS

被引：7

作者：

FUJII, S

FUKUMOTO, M

FUSE, G

OHZONE, T

机构：

来源：

关键词：

D O I：

10.1109/16.7393

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：1829 / 1833

页数：5

共 11 条

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HAZUKI, Y
MORIYA, T
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1987, 34 (03) : 628 - 632
[4] HAZUKI Y, 1985, S VLSI TECH, P20
[5] Kotani H., 1987, S VLSI CIRCUITS, P87
[6] SIO2 PLANARIZATION TECHNOLOGY WITH BIASING AND ELECTRON-CYCLOTRON RESONANCE PLASMA DEPOSITION FOR SUBMICRON INTERCONNECTIONS
MACHIDA, K
OIKAWA, H
[J]. JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1986, 4 (04): : 818 - 821
[7] MACHIDA K, 1987, S VLSI TECH, P69
[8] MISAWA Y, 1986, S VLSI TECH, P59
[9] MORIMOTO M, 1983, S VLSI TECH, P100
[10] 2-LAYER PLANARIZATION PROCESS
SCHILTZ, A
PONS, M
[J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1986, 133 (01) : 178 - 181