DETECTION OF INTERFACE AND VOLUME TRAPS IN VERY THIN OXIDE MOS STRUCTURES USING DLTS, QUASI-STATIC AND CONDUCTANCE MEASUREMENTS

Electrically active interface and volume traps in Cr-SiO2-Si (p-type) capacitors with very thin oxide layers (3.5 and 8.5 nm) are studied. The determination of the interface trap parameters is performed using three techniques; quasi-static, conductance and deep level transient spectroscopy (DLTS). Their densities are typically in the range of 10(10) eV-1 cm-2 near the silicon midgap for 8.5 nm thick oxide layers and of 10(11) eV-1 cm2 for 3.5 nm thick oxide layers. Furthermore these different techniques are compared in detail. Concerning the volume traps, DLTS allows the determination of their energy location and capture cross-section. Such traps are found at 300 meV above the valence band. Complementary results on these traps are obtained by taking into account' conductance technique measurements in the strong inversion regime.