YIELD ANALYSIS OF LARGE INTEGRATED CIRCUIT CHIPS

It has been experimentally observed that integrated-circuit yields decrease as their size increases and various attempts have been made to explain the variation. This paper analyzes yield in terms of the geometrical factors involved in producing large chips from circular slices. It is shown that the qualitatively correct dependence of yield on area is obtained when a defect density that is higher near the outside of the slice is assumed. Results of computer program calculations of the maximum possible number of chips that can be obtained from a slice are given, assuming both random and nonrandom defect distributions.