AN EFFICIENT MICROCODE COMPILER FOR APPLICATION SPECIFIC DSP PROCESSORS

被引：23

作者：

GOOSSENS, G

RABAEY, J

VANDEWALLE, J

DEMAN, H

机构：

[1] UNIV CALIF BERKELEY,DEPT ELECT ENGN & COMP SCI,BERKELEY,CA 94720

[2] CATHOLIC UNIV LEUVEN,ESAY LAB,B-3030 HEVERLE,BELGIUM

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1990年 / 9卷 / 09期

关键词：

D O I：

10.1109/43.59069

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a computer program for microcode compilation for custom digital signal processors is presented. This tool is part of the CATHEDRAL II silicon compiler. The following optimization problems are highlighted: scheduling, hardware assignment, and loop folding. Efficient techniques are developed to solve these problems. This allows for the automatic synthesis of processor architectures which simultaneously exploit pipelining and parallelism. A demonstrator design is presented in the paper. © 1990 IEEE

引用

页码：925 / 937

页数：13

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[21] FORCE-DIRECTED SCHEDULING FOR THE BEHAVIORAL SYNTHESIS OF ASICS [J].