Josephson Edge-Triggered Gates for Sequential Circuits

A Josephson sequential logic family with very wide operating margin (+/- 67%) and insensitivity to global parameter-variations is proposed. Derived from the original idea of edge-triggered latching comparator by Hamilton et al. [1], this logic gate consists of a pair of conventional gates in series biased by a delay clock. In the normal operation, switching occurs in one gate which has smaller critical current. Unlike most other Josephson logic gates, where switching occurs when gate current is larger than critical current, the switching is determined by comparison of the critical currents of two gates, and therefore a global control of critical-current variations is not important. The speed of this edge-triggered gate is comparable to or even faster than other latch gates with three-phase clocking because a two-phase clock can be used, which saves one gate delay, and a short reset time is provided by a Small shunting resistor. We have built and tested a few circuits to illustrate this logic gate design: a 32-bit shift register designed by OR gates with +/- 42% bias margin and +/- 89% input margin, a 4-bit pseudorandom sequence generator designed by exclusive-on gates with +/- 27% bias margin and +/- 78% input margin, and a cross-section of a 6-bit NOR gate decoder with +/- 33% bias margin.