JOSEPHSON 4 K-BIT CACHE MEMORY DESIGN FOR A PROTOTYPE SIGNAL PROCESSOR .1. GENERAL OVERVIEW

被引：5

作者：

HENKELS, WH

GEPPERT, LM

KADLEC, J

EPPERLEIN, PW

BEHA, H

CHANG, WH

JAECKEL, H

机构：

来源：

JOURNAL OF APPLIED PHYSICS | 1985年 / 58卷 / 06期

关键词：

D O I：

10.1063/1.335960

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

引用

页码：2371 / 2378

页数：8

共 16 条

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[7] JOSEPHSON 4 K-BIT CACHE MEMORY DESIGN FOR A PROTOTYPE SIGNAL PROCESSOR .3. DECODING, SENSING, AND TIMING [J].

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[8] JOSEPHSON 4 K-BIT CACHE MEMORY DESIGN FOR A PROTOTYPE SIGNAL PROCESSOR .2. CELL ARRAY AND DRIVERS [J].

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[10]

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