JOSEPHSON 4 K-BIT CACHE MEMORY DESIGN FOR A PROTOTYPE SIGNAL PROCESSOR .3. DECODING, SENSING, AND TIMING

被引：6

作者：

HENKELS, WH

GEPPERT, LM

KADLEC, J

EPPERLEIN, PW

BEHA, H

CHANG, WH

JAECKEL, H

机构：

来源：

JOURNAL OF APPLIED PHYSICS | 1985年 / 58卷 / 06期

关键词：

D O I：

10.1063/1.336303

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

引用

页码：2389 / 2399

页数：11

共 15 条

[1]

ANDERSON CC, COMMUNICATION

[2] POWER DESIGN FOR GIGABIT JOSEPHSON LOGIC SYSTEMS [J].

ARNETT, PC ;

HERRELL, DJ .

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, 1980, 28 (05) :500-508

[3] JOSEPHSON DEVICE WITH WELL-DEFINED AND LOW CRITICAL-POINTS [J].

BEHA, H .

IEEE TRANSACTIONS ON MAGNETICS, 1983, 19 (03) :1229-1233

[4] HIGH-TOLERANCE 3-JOSEPHSON-JUNCTION CURRENT-INJECTION LOGIC DEVICES (HTCID) [J].

BEHA, H ;

JACKEL, H .

IEEE TRANSACTIONS ON MAGNETICS, 1981, 17 (06) :3423-3425

[5] BASIC DESIGN OF A JOSEPHSON-TECHNOLOGY CACHE MEMORY [J].

FARIS, SM ;

HENKELS, WH ;

VALSAMAKIS, EA ;

ZAPPE, HH .

IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1980, 24 (02) :143-154

[6] DESIGN OF 2.5-MICROMETER JOSEPHSON CURRENT INJECTION LOGIC (CIL) [J].

GHEEWALA, TR .

IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1980, 24 (02) :130-142

[7] PUNCHTHROUGH ANALYSIS OF JOSEPHSON LOGIC-CIRCUITS [J].

HARRIS, EP ;

CHANG, WH .

IEEE TRANSACTIONS ON MAGNETICS, 1983, 19 (03) :1209-1212

[8] JOSEPHSON 4 K-BIT CACHE MEMORY DESIGN FOR A PROTOTYPE SIGNAL PROCESSOR .1. GENERAL OVERVIEW [J].

HENKELS, WH ;

GEPPERT, LM ;

KADLEC, J ;

EPPERLEIN, PW ;

BEHA, H ;

CHANG, WH ;

JAECKEL, H .

JOURNAL OF APPLIED PHYSICS, 1985, 58 (06) :2371-2378

[9] JOSEPHSON 4 K-BIT CACHE MEMORY DESIGN FOR A PROTOTYPE SIGNAL PROCESSOR .2. CELL ARRAY AND DRIVERS [J].

HENKELS, WH ;

GEPPERT, LM ;

KADLEC, J ;

EPPERLEIN, PW ;

BEHA, H ;

CHANG, WH ;

JAECKEL, H .

JOURNAL OF APPLIED PHYSICS, 1985, 58 (06) :2379-2388

[10]

HENKELS WH, UNPUB

← 1 2 →