SILICON HYBRID WAFER-SCALE PACKAGE TECHNOLOGY

被引：16

作者：

JOHNSON, RW

DAVIDSON, JL

JAEGER, RC

KERNS, DV

机构：

来源：

关键词：

D O I：

10.1109/JSSC.1986.1052616

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：845 / 851

页数：7

共 56 条

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[2]

AMEY DI, 1982, ELECTRON PACKAGI JAN, P262

[3]

Arthur D. J., 1985, Fifth Annual International Electronics Packaging Conference. Proceedings of the Technical Conference, P571

[4]

Aubusson R. C., 1978, Microelectronics, V9, P5

[5] WAFER-SCALE INTEGRATION - FAULT-TOLERANT PROCEDURE [J].

AUBUSSON, RC ;

CATT, I .

[6] ANISOTROPIC ETCHING OF SILICON [J].

BEAN, KE .

BEGG, IM .

IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY, 1981, 4 (01) :154-157

[8]

BIANCOMANO V, 1986, ELECTRON DESIGN APR, P110

[9]

BURNS CD, 1979, SEMICONDUCTOR IN APR, P25

[10]

CALHOUN DF, 1969, AFIPS C P, V35, P99