A HIGH-SPEED DIGITAL NEURAL NETWORK CHIP WITH LOW-POWER CHAIN-REACTION ARCHITECTURE

A high-speed digital neural network chip adopts a polyhedric discrimination neuron (PDN) model and low-power chain-reaction (LCR) architecture that can reduce the power dissipation to one-fiftieth or less. The chip contains 832 fully implemented digital synapse units that form 13 neurons on a 10.3 x 14.1-mm2 die using 0.8-mum CMOS technology. The synapse weights are updated using an external computer. A computational speed of 8 billion connections per second (GCPS) is achieved with low 54-mW power dissipation. The forward propagation time is 104 ns. These features make it possible to implement large-scale neural network chips and systems.