SCALING I2L FOR VLSI

Scaling integrated injection logic for high-density VLSI circuits is discussed. The basic principles governing the operation of an I2L device and the impact of specific process/design changes on performance are reviewed. A procedure for scaling I2L devices with geometries =1 μm is described and examples of scaled devices fabric ited with e-beam slice writing techniques are given. It is shown that the I2L gate propagation delay can be scaled over the entire range of operating currents through a combination of scaling and sizing. The physical limitations that apply to submkron geometries are summarized and the performance attainable with a submicron device design is predicted. Copyright © 1979 by The Institute of Electrical and Electronics Engineers, Inc.