SIMULTANEOUS DELAY AND MAXIMUM CURRENT CALCULATION IN CMOS GATES

被引：3

作者：

NABAVILISHI, A

RUMIN, NC

机构：

[1] Electrical Eng., McGill University, Montreal, Quebec H3A 2A7

来源：

ELECTRONICS LETTERS | 1992年 / 28卷 / 07期

关键词：

MODELING; INTEGRATED CIRCUITS;

D O I：

10.1049/el:19920431

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An accurate and simple technique is presented for computing the delay and the maximum switching current in CMOS gates. The effects of input slope, output load, transistor size, and short circuit current are accounted for. The accuracy is within 10% of the SPICE level-3 model and the speed is more than three orders of magnitude faster than SPICE.

引用

页码：682 / 684

页数：3

共 4 条

[1] ESTIMATION OF MAXIMUM CURRENTS IN MOS IC LOGIC-CIRCUITS [J].