A 25-NS LOW-POWER FULL-CMOS 1-MBIT (128K X 8) SRAM

被引：6

作者：

CHU, ST ^{[1
]}

DIKKEN, J ^{[1
]}

HARTGRING, CD ^{[1
]}

LIST, FJ ^{[1
]}

RAEMAEKERS, JG ^{[1
]}

BELL, SA ^{[1
]}

WALSH, B ^{[1
]}

SALTERS, RHW ^{[1
]}

机构：

[1] SILICON & SOFTWARE SYST,DUBLIN 18,IRELAND

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1988年 / 23卷 / 05期

关键词：

DATA STORAGE; SEMICONDUCTOR -- Storage Devices - SEMICONDUCTOR DEVICES; MOS;

D O I：

10.1109/4.5928

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 5-V full-CMOS 1-Mb SRAM (static random-access memory) is described. The access time is 25 ns with 30-pF load, and power dissipation is 75 mW at 10 MHz and less than 1 μW in standby mode. The chip is made in a 0.7-μm twin-tub, single-poly, double-metal technology on p/p+ epi substrate. Cascoding of NMOS devices and special timing techniques are used to suppress hot-electron degradation. The authors describe circuit techniques that obtain low active power dissipation and high speed for a byte-wide part.

引用

页码：1078 / 1084

页数：7

共 8 条

[1]

DEWERDT R, 1987, DEC IEDM, P532

[2] A 40-NS/100-PF LOW-POWER FULL-CMOS 256K (32KX8) SRAM [J].

GUBBELS, WCH ;

HARTGRING, CD ;

SALTERS, RHW ;

LAMMERTS, JAM ;

TOOHER, MJ ;

HENS, PFPC ;

BASTIAENS, JJJ ;

VANDIJK, JMF ;

SPROKEL, MA .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (05) :741-747

[3]

HARDEE K, 1984, FEB ISSCC, P216

[4] A 25-NS 1-MBIT CMOS SRAM WITH LOADING-FREE BIT LINES [J].

MATSUI, M ;

OHTANI, T ;

TSUJIMOTO, JI ;

IWAI, H ;

SUZUKI, A ;

SATO, K ;

ISOBE, M ;

HASHIMOTO, K ;

SAITOH, M ;

SHIBATA, H ;

SASAKI, H ;

MATSUNO, T ;

MATSUNAGA, JI ;

IIZUKA, T .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (05) :733-740

[5] STATIC-NOISE MARGIN ANALYSIS OF MOS SRAM CELLS [J].

SEEVINCK, E ;

LIST, FJ ;

LOHSTROH, J .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (05) :748-754

[6]

WADA E, 1987, IEEE J SOLID STATE C, V22, P727

[7]

YANEY DS, 1985, DEC IEDM WASH, P698

[8] A DIVIDED WORD-LINE STRUCTURE IN THE STATIC RAM AND ITS APPLICATION TO A 64K FULL CMOS RAM [J].

YOSHIMOTO, M ;

ANAMI, K ;

SHINOHARA, H ;

YOSHIHARA, T ;

TAKAGI, H ;

NAGAO, S ;

KAYANO, S ;

NAKANO, T .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1983, 18 (05) :479-485

← 1 →