A 25-NS 1-MBIT CMOS SRAM WITH LOADING-FREE BIT LINES

被引：13

作者：

MATSUI, M ^{[1
]}

OHTANI, T ^{[1
]}

TSUJIMOTO, JI ^{[1
]}

IWAI, H ^{[1
]}

SUZUKI, A ^{[1
]}

SATO, K ^{[1
]}

ISOBE, M ^{[1
]}

HASHIMOTO, K ^{[1
]}

SAITOH, M ^{[1
]}

SHIBATA, H ^{[1
]}

SASAKI, H ^{[1
]}

MATSUNO, T ^{[1
]}

MATSUNAGA, JI ^{[1
]}

IIZUKA, T ^{[1
]}

机构：

[1] TOSHIBA CORP,DIV INTEGRATED CIRCUIT,KAWASAKI 210,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1987年 / 22卷 / 05期

关键词：

D O I：

10.1109/JSSC.1987.1052807

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：733 / 740

页数：8

共 10 条

[1] 2 13-NS 64K CMOS SRAMS WITH VERY LOW ACTIVE POWER AND IMPROVED ASYNCHRONOUS CIRCUIT TECHNIQUES [J].

FLANNAGAN, ST ;

REED, PA ;

VOSS, PH ;

NOGLE, SG ;

DAY, LJ ;

SHENG, DY ;

BARNES, JJ ;

KUNG, RI .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (05) :692-703

[2] A FAULT-TOLERANT 30 NS-375 MW 16KX1 NMOS STATIC RAM [J].

HARDEE, KC ;

SUD, R .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1981, 16 (05) :435-443

[3]

Kinugawa M., 1985, 1985 Symposium on VLSI Technology. Digest of Technical Papers, P116

[4] A 10-MU W STANDBY POWER 256K CMOS SRAM [J].

KOBAYASHI, Y ;

EGUCHI, H ;

KUDOH, O ;

HARA, T ;

OOKA, H ;

SASAKI, I ;

ANDOH, M ;

TAMEDA, M .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (05) :935-940

[5]

MINATO O, 1984, FEB ISSCC, P222

[6] 1-MBIT VIRTUALLY STATIC RAM [J].

NOGAMI, K ;

SAKURAI, T ;

SAWADA, K ;

WADA, T ;

SATO, K ;

ISOBE, M ;

KAKUMU, M ;

MORITA, S ;

YOKOGAWA, S ;

KINUGAWA, M ;

ASAMI, T ;

HASHIMOTO, K ;

MATSUNAGA, JI ;

NOZAWA, H ;

IIZUKA, T .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (05) :662-669

[7] A LOW-POWER 46 NS 256 KBIT CMOS STATIC RAM WITH DYNAMIC DOUBLE WORD LINE [J].

SAKURAI, T ;

MATSUNAGA, J ;

ISOBE, M ;

OHTANI, T ;

SAWADA, K ;

AONO, A ;

NOZAWA, H ;

IIZUKA, T ;

KOHYAMA, S .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1984, 19 (05) :578-585

[8]

SAKURAI T, 1982, OCT P COMM SOL STAT, P15

[9]

SHIBATA H, 1987, 1987 P S VLSI TECH

[10] A 256K CMOS SRAM WITH VARIABLE IMPEDANCE DATA-LINE LOADS [J].

YAMAMOTO, S ;

TANIMURA, N ;

NAGASAWA, K ;

MEGURO, S ;

YASUI, T ;

MINATO, O ;

MASUHARA, T .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1985, 20 (05) :924-928

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