A 10-MU W STANDBY POWER 256K CMOS SRAM

被引:4
作者
KOBAYASHI, Y
EGUCHI, H
KUDOH, O
HARA, T
OOKA, H
SASAKI, I
ANDOH, M
TAMEDA, M
机构
关键词
D O I
10.1109/JSSC.1985.1052418
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:935 / 940
页数:6
相关论文
共 8 条
[1]  
AKATSUKA Y, 1980, 6TH EUR SOL STAT CIR, P155
[2]   A HI-CMOSII 8K-BY-8 BIT STATIC RAM [J].
MINATO, O ;
MASUHARA, T ;
SASAKI, T ;
SAKAI, Y ;
HAYASHIDA, T ;
NAGASAWA, K ;
NISHIMURA, K ;
YASUI, T .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1982, 17 (05) :793-797
[3]  
MINATO O, 1984, FEB ISSCC, P222
[4]   AN ULTRALOW POWER 8K-BY-8-BIT FULL CMOS RAM WITH A 6-TRANSISTOR CELL [J].
OCHII, K ;
HASHIMOTO, K ;
YASUDA, H ;
MASUDA, M ;
KONDO, T ;
NOZAWA, H ;
KOHYAMA, S .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1982, 17 (05) :798-803
[5]   A LOW-POWER 46 NS 256 KBIT CMOS STATIC RAM WITH DYNAMIC DOUBLE WORD LINE [J].
SAKURAI, T ;
MATSUNAGA, J ;
ISOBE, M ;
OHTANI, T ;
SAWADA, K ;
AONO, A ;
NOZAWA, H ;
IIZUKA, T ;
KOHYAMA, S .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1984, 19 (05) :578-585
[6]   A LOW-POWER RESISTIVE LOAD 64 KBIT CMOS-RAM [J].
UCHIDA, Y ;
IIZUKA, T ;
MATSUNAGA, J ;
ISOBE, M ;
KONISHI, S ;
SEKINE, M ;
OHTANI, T ;
KOHYAMA, S .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1982, 17 (05) :804-809
[7]   A BATTERY BACKUP 64K CMOS RAM WITH DOUBLE-LEVEL ALUMINUM TECHNOLOGY [J].
WATANABE, T ;
HAYASI, M ;
SASAKI, I ;
AKATSUKA, Y ;
TSUJIDE, T ;
YAMAMOTO, H ;
KUDOH, O ;
TAKAHASHI, S ;
HARA, T .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1983, 18 (05) :494-498
[8]   A 25 NS 64K STATIC RAM [J].
YAMANAKA, T ;
KOSHIMARU, S ;
KUDOH, O ;
OZAWA, Y ;
YASUOKA, N ;
ITO, H ;
ASAI, H ;
HARASHIMA, N ;
KIKUCHI, S .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1984, 19 (05) :572-577