THE EFFECT OF SILICON GATE MICROSTRUCTURE AND GATE OXIDE PROCESS ON THRESHOLD VOLTAGE INSTABILITIES IN P+-GATE P-CHANNEL MOSFETS WITH FLUORINE INCORPORATION

Several phenomena have been identified which significantly reduce boron penetration for boron difluoride-implanted or boron/fluorine-co-implanted gates. The fluorine-induced threshold-voltage (V(TP)) shift is minimized by using an as-deposited amorphous silicon gate and a gate oxide process that excludes hydrogen chloride. The V(TP) shift can be reduced to a level close to that of a boron-implanted gate, while maintaining the fluorine incorporation at the SiO2/Si interface to lower interface-state density. A model based on the fluorine atom distribution is proposed to explain the observed V(TP) shift.