A 10-B, 20 M-SAMPLE/S, 35-MW PIPELINE A/D CONVERTER

被引:387
作者
CHO, TB
GRAY, PR
机构
[1] Department of Electrical Engineering and Computer Sciences, University of California, Berkeley
基金
美国国家科学基金会;
关键词
D O I
10.1109/4.364429
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper describes a 10 b, 20 Msample/s pipeline AID converter implemented in 1.2 mu m CMOS technology which achieves a power dissipation of 35 mW at full speed operation, Circuit techniques used to achieve this level of power dissipation include digital correction to allow the use of dynamic comparators, and optimum scaling of capacitor values through the pipeline, Also, to be compatible with low voltage mixed-signal system environments, a switched capacitor (SC) circuit in each pipeline stage is implemented and operated at 3.3 V with a new high-speed, low-voltage operational amplifier and charge pump circuits, Measured performance includes 0.6 LSB of INL, 59.1 dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 100 kHz input at 20 Msample/s, At Nyquist sampling (10 MHz input), SNDR is 55.0 dB, Differential input range is +/- V, and measured input referred RMS noise is 220 mu V. The power dissipation at 1 MS/s is below 3 mW with 58 dB of SNDR.
引用
收藏
页码:166 / 172
页数:7
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