REPROGRAMMABLE GATE ARRAYS FOR HARDWARE ACCELERATED IC DESIGN VERIFICATION

The paper discusses the development of a hardware accelerator environment for ASIC design verification. A reprogrammable gate array serves as a breadboard for the ASIC design. Design entry is accepted in schematic or VHDL description form. An IC test instrument is used to program the gate array and run realtime functional tests on the ASIC design. It is anticipated that significant reductions in the ASIC development cycle can be achieved with this system, as well as allowing for more rapid design space exploration. Hardware accelerated logic and fault simulation is also accommodated when the reprogrammable gate array is configured as either the faulty or fault-free logic block of interest. © 1990.