LATERAL CHARGE TRANSPORT FROM HEAVY-ION TRACKS IN INTEGRATED-CIRCUIT CHIPS

A 256K DRAM has been used to study the lateral transport of charge (electron-hole pairs) induced by direct ionization from heavy-ion tracks in an IC. The qualitative charge transport has been simulated using a 2-D numerical code in cylindrical coordinates. The experimental bit-map data clearly show the manifestation of lateral charge transport in the creation of adjacent multiple-bit errors from a single heavy-ion track. The heavy-ion data further demonstrate the occurrence of multiple-bit errors from single ion tracks with sufficient stopping power. The qualitative numerical simulation results suggest that electric-field-funnel-aided (drift) collection accounts for single error generated by an ion passing through a charge-collecting junction, while multiple errors from a single ion track are due to lateral diffusion of ion-generated charge. A quantitative analysis of this effect would require that the simulation be extended to adjacent devices and would therefore require a 3-D numerical code in Cartesian coordinates.