CHARACTERIZATION, MODELING, AND MINIMIZATION OF TRANSIENT THRESHOLD VOLTAGE SHIFTS IN MOSFETS

MOSFET's subjected to large-signal gate-source voltage pulses on microsecond to millisecond time scales exhibit transient threshold voltage shifts which relax over considerably longer periods of time. This problem is important in high-accuracy analog circuits where it can cause errors at the 12 b level and above. In this paper, transient threshold voltage shifts are characterized with respect to their dependence on stress amplitude and duration, relaxation time, gate bias, substrate bias, drain voltage, temperature, and channel width and length. In contrast to previous studies, threshold voltage shifts are measured at time and voltage scales relevant to analog circuits, and are shown to occur even when the effects of Fowler-Nordheim tunneling, avalanche injection, hot carriers, trap generation, self-heating, mobile ions, and dipolar polarizations are absent. A new model is proposed in which channel charge carriers tunnel to and from near-interface oxide traps by one of three parallel pathways. Transitions may occur elastically, by direct tunneling between the silicon band edges and an oxide trap, or inelastically, by tunneling in conjunction with a thermal transition in the insulator or at the Si-SiO2 interface. Simulations based on this model show excellent agreement with experimental results. The threshold voltage shifts are also shown to be correlated with 1/f noise, in corroboration of the tunneling model. Techniques for the minimization and modeling of errors in circuits are presented.