THE IMPACT OF N- DRAIN LENGTH AND GATE DRAIN SOURCE OVERLAP ON SUBMICROMETER LDD DEVICES FOR VLSI

被引：15

作者：

IZAWA, R

TAKEDA, E

机构：

来源：

IEEE ELECTRON DEVICE LETTERS | 1987年 / 8卷 / 10期

关键词：

D O I：

10.1109/EDL.1987.26701

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：480 / 482

页数：3

共 8 条

[1] ASYMMETRICAL CHARACTERISTICS IN LDD AND MINIMUM-OVERLAP MOSFETS [J].

CHAN, TY ;

WU, AT ;

KO, PK ;

HU, CM ;

RAZOUK, RR .

IEEE ELECTRON DEVICE LETTERS, 1986, 7 (01) :16-19

[2]

Hamamoto T., 1986, 1986 Symposium on VLSI Technology. Digest of Technical Papers, P67

[3] STRUCTURE-ENHANCED MOSFET DEGRADATION DUE TO HOT-ELECTRON INJECTION [J].

HSU, FC ;

GRINOLDS, HR .

IEEE ELECTRON DEVICE LETTERS, 1984, 5 (03) :71-74

[4]

Katto H., 1984, International Electron Devices Meeting. Technical Digest (Cat. No. 84CH2099-0), P774

[5]

Ko P. K., 1986, International Electron Devices Meeting 1986. Technical Digest (Cat. No.86CH2381-2), P292

[6]

Mayaram K., 1986, 1986 Symposium on VLSI Technology. Digest of Technical Papers, P61

[7] AN ANALYTICAL MODEL FOR THE CHANNEL ELECTRIC-FIELD IN MOSFETS WITH GRADED-DRAIN STRUCTURES [J].

TERRILL, KW ;

HU, C ;

KO, PK .

IEEE ELECTRON DEVICE LETTERS, 1984, 5 (11) :440-442

[8] 3-DIMENSIONAL DEVICE SIMULATOR CADDETH WITH HIGHLY CONVERGENT MATRIX SOLUTION ALGORITHMS [J].

TOYABE, T ;

MASUDA, H ;

AOKI, Y ;

SHUKURI, H ;

HAGIWARA, T .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1985, 4 (04) :482-488

← 1 →