TRENDS IN LOW-POWER RAM CIRCUIT TECHNOLOGIES

Trends in low-power circuit technologies of CMOS RAM chips are reviewed in terms of three key issues: charging capacitance, operating voltage, and de current. The discussion includes a general description of power sources in a RAM chip, and covers both DRAM's and SRAM's. In DRAM's, successive circuit advancements have produced a power reduction equivalent to two to three orders of magnitude over the East decade for a fired memory capacity chip. Coupled with the low-power advantage of CMOS circuits, two technologies have been the major contributors to power reduction: lower charging capacitance due to partial activation of multi-divided arrays that use multi-divisions of data and word lines; and lower operating voltage resulting from external power supply reduction, half-V-DD precharging, and on-chip voltage down converting scheme. In SRAM's, partial activation of a multi-divided word line drastically reduces the de current from the data-line load to the selected cell. In addition to advances in the sense amplifier circuit an auto power down scheme that uses address transition detection for word driver and column circuitry further reduces the de current. It is also shown that to design ultralow voltage DRAM's and SRAM's, the application of subthreshold current reduction circuits (such as source-gate back biasing) to cell and iterative circuit blocks will be indispensable in the future.