High-performance fully depleted silicon-nanowire (diameter ≤ 5 nm) gate-all-around CMOS devices

被引：540

作者：

Singh, N. ^{[1
]}

Agarwal, A. ^{[1
]}

Bera, L. K. ^{[1
]}

Liow, T. Y. ^{[1
]}

Yang, R. ^{[1
]}

Rustagi, S. C. ^{[1
]}

Tung, C. H. ^{[1
]}

Kumar, R. ^{[1
]}

Lo, G. Q. ^{[1
]}

Balasubramanian, N. ^{[1
]}

Kwong, D. -L. ^{[1
]}

机构：

[1] Inst Microelect, Singapore 117685, Singapore

来源：

IEEE ELECTRON DEVICE LETTERS | 2006年 / 27卷 / 05期

关键词：

CMOS-compatible process; gate-all-around (GAA); silicon nanowire transistor; surround gate; wrap-around-gate;

D O I：

10.1109/LED.2006.873381

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with <= 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g-, near ideal subthreshold slope (similar to 63 mWdec), low drain-induced barrier lowering (similar to 10 V/V), and with I-ON/I-OFF ratio of similar to 10(6). High drive currents of similar to 1.5 and similar to 1.0 mA/mu m were achieved for 180-nm-long n- and p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.

引用

页码：383 / 386

页数：4

共 21 条

[1] Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFET's [J].