An error control code scheme for multilevel Flash memories

被引：6

作者：

Gregori, S ^{[1
]}

Khouri, O ^{[1
]}

Micheloni, R ^{[1
]}

Torelli, G ^{[1
]}

机构：

[1] Univ Pavia, Dept Elect, I-27100 Pavia, Italy

来源：

2001 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING, PROCEEDINGS | 2001年

关键词：

D O I：

10.1109/MTDT.2001.945227

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a new scheme for error control coding in multilevel Flash memories. The n bits stored in a single memory cell are organized in different "bit-layers", which are independent from one another. Error correction is carried out separately, for each bit-layer. The correction of any failure in a single memory cell is therefore achieved by using a simple error control code (ECC) providing single-bit correction, regardless of the number of bits stored in a single cell. This greatly simplifies the encoding and decoding circuits and minimizes the impact of ECC time overhead on memory access time. Moreover the same encoding/decoding circuit and check cells are used with multilevel memories working at a variable number of bits per cell.

引用

页码：45 / 49

页数：5

共 8 条

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