Study of fluctuations in advanced MOSFETs using a 3D finite element parallel simulator

Two important new sources of fluctuations in nanoscaled MOSFETs are the polysilicon gates and the introduction of high-kappa gate dielectrics. Using a 3D parallel drift-diffusion device simulator, we study the influence of the polycrystal grains in polysilicon and in the high-kappa dielectric on the device threshold for MOSFETs with gate lengths of 80 and 25 nm. We model the surface potential pinning at the grain boundaries in polysilicon through the inclusion of an interfacial charge between the grains. The grains in the high-kappa gate dielectric are distinguished by different dielectric constants. We have found that the largest impact of the polysilicon grain boundary in the 80 nm gate length MOSFET occurs when it is positioned perpendicular to the current flow. At low drain voltage the maximum impact occurs when the grain boundary is close to the middle of the gate. At high drain voltage the impact is stronger when the boundary is moved toward the source end of the channel. Similar behaviour is observed in the 25 nm gate length MOSFET.