Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering

Local voltage dithering provides near optimum savings when workload varies for fine-grained blocks. Combining this approach with sub-threshold operation permits ultra-dynamic voltage scaling from 1.1 V to below 300 mV for a 90-nm test chip. Operating at 330 mV provides minimum energy per cycle at 9X less energy than ideal shutdown for reduced performance scenarios. Measurements from the test chip characterize the impact of temperature on the minimum energy point.