Ultra-low resistance, through-wafer via (TWV) technology and its applications in three dimensional structures on silicon

This paper presents an ultra-low resistance, high wiring density, through-wafer via (TWV) technology that is compatible with standard silicon wafer processing. Vias as small as 30 mu m by 30 mu m are fabricated through a 525 mu m thick wafer This results in an aspect ratio for the via that is greater than 17:1. Furthermore, the de resistance of a single via is less than 50 m Ohm. Key fabrication steps, including the silicon dry etch, copper metallization, and photoresist electroplating, are described in detail. As a demonstration of the potential applications of the TWV technology, a novel three dimensional inductor is designed and fabricated. For a 0.9-nH inductor, a quality factor of 18.5 is measured at 800 MHz.