A fully integrated on-chip dc-dc conversion and power management system

被引：123

作者：

Patounakis, G ^{[1
]}

Li, YW ^{[1
]}

Shepard, KL ^{[1
]}

机构：

[1] Columbia Univ, Dept Elect Engn, Columbia Integrated Syst Lab, New York, NY 10027 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2004年 / 39卷 / 03期

基金：

美国国家科学基金会;

关键词：

dc-to-dc converter; low power; power management; regulator;

D O I：

10.1109/JSSC.2003.822773

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

It is widely recognized that adaptive control of the power supply is one of the most effective variables to achieve energy-efficient computation. Most on-chip dc-dc conversion systems have relied on buck converters with off-chip LC filters. In this paper, we describe the development of a software controllable, fully integrated on-chip dc-dc downconversion system that combines switched-capacitor voltage dividers and linear regulators to efficiently regulate from 2.5 V down to about 0.65 V. The use of switched-capacitor supplies offers better efficiencies than what is achievable with linear regulators alone.

引用

页码：443 / 451

页数：9

共 15 条

[1] Design issues for dynamic voltage scaling [J].

Burd, TD ;

Brodersen, RW .

ISLPED '00: PROCEEDINGS OF THE 2000 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, 2000, :9-14

[2]

Carley L. R., 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477), P109, DOI 10.1109/LPE.1999.799423

[3] High-efficiency multiple-output DC-DC conversion for low-voltage systems [J].

Dancy, AP ;

Amirtharajah, R ;

Chandrakasan, AP .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2000, 8 (03) :252-263

[4] Embedded 5 V to 3.3 V voltage regulator for supplying digital IC's in 3.3 V CMOS technology [J].

den Besten, GW ;

Nauta, B .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (07) :956-962

[5]

DRAGONE N, 2000, P INT S LOW POW EL D, P20

[6] On-chip voltage down converter for low-power digital system [J].

Jou, SJ ;

Chen, TS .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1998, 45 (05) :617-625

[7] Managing power and performance for System-on-Chip designs using voltage islands [J].

Lackey, DE ;

Zuchowski, PS ;

Bednar, TR ;

Stout, DW ;

Gould, SW ;

Cohn, JM .

IEEE/ACM INTERNATIONAL CONFERENCE ON CAD-02, DIGEST OF TECHNICAL PAPERS, 2002, :195-202

[8] Low-power area-efficient high-speed I/O circuit techniques [J].

Lee, MJE ;

Dally, WJ ;

Chiang, P .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (11) :1591-1599

[9]

Li YW, 2003, 2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, P49

[10]

QU G, 1999, P IEEE INT S CIRCUIT, V1, P362

← 1 2 →