The effect of annealing temperatures on self-aligned replacement (damascene) TaCN-TaN-stacked gate pMOSFETs

In this paper, we report the first self-aligned replacement (Damascene) TaCN-TaN-stacked gate electrode pMOSFETs. The high-temperature (> 1000 degreesC) implant activation anneal was done prior to the metal electrode deposition. After the fabrication was completed, the transistors were then annealed at lower temperatures (300degreesC-600degreesC), which might affect the critical device parameters, such as subthreshold slope, threshold voltage, gate leakage, on, and off currents. Our data show that TaCN is a promising material for the metal-gate pMOSFETs due to the suitable metal work function and good thermal stability up to 500 degreesC, which is much higher than the highest temperature required by the backend very large-scale integration process.