Two-dimensional parallel pipeline smart pixel array cellular logic (SPARCL) processors - Chip design and system implementation

被引：5

作者：

Kunzia, CB ^{[1
]}

Wu, JM ^{[1
]}

Chen, CH ^{[1
]}

Hoanca, B ^{[1
]}

Cheng, L ^{[1
]}

Weber, AG ^{[1
]}

Sawchuk, AA ^{[1
]}

机构：

[1] Univ So Calif, Inst Signal & Image Proc, Los Angeles, CA 90089 USA

来源：

IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS | 1999年 / 5卷 / 02期

基金：

美国国家科学基金会;

关键词：

cellular logic arrays; CMOS integrated circuits; integrated optoelectronics; optical interconnections; smart pixels;

D O I：

10.1109/2944.778326

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We describe the chip design and system implementation of an optoelectronic parallel pipeline processing system composed of cascaded stages of smart pixel array cellular logic (SPARCL) processors interconnected with free-space digital optic channels. The SPARCL processing elements are arranged in a two-dimensional array, and each contains an independent optical input/output port and electrical nearest-neighbor local interconnections. The smart pixels are implemented using GaAs-GaAlAs multiple quantum-well diode arrays flip-chip bonded onto complementary metal-oxide-semiconductor circuitry through the Bell Labs Lucent Technologies/George Mason University optoelectronic VLSI foundry, This system provides efficient execution of single-instruction multiple-data algorithms on large data fields and images.

引用

页码：376 / 386

页数：11

共 31 条

[1]

BATCHER KE, 1980, IEEE T COMPUT, V29, P836, DOI 10.1109/TC.1980.1675684

[2] Performance evaluation and optimization in low-cost cellular SIMD systems [J].

Broggi, A ;

Gregoretti, F .

MICROPROCESSING AND MICROPROGRAMMING, 1996, 41 (8-9) :659-678

[3] An ATM-based intelligent optical backplane using CMOS-SEED smart pixel arrays and free-space optical interconnect modules [J].

Goodwill, DJ ;

Devenport, KE ;

Hinton, HS .

IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS, 1996, 2 (01) :85-96

[4] GAAS MQW MODULATORS INTEGRATED WITH SILICON CMOS [J].

GOOSSEN, KW ;

WALKER, JA ;

DASARO, LA ;

HUI, SP ;

TSENG, B ;

LEIBENGUTH, R ;

KOSSIVES, D ;

BACON, DD ;

DAHRINGER, D ;

CHIROVSKY, LMF ;

LENTINE, AL ;

MILLER, DAB .

IEEE PHOTONICS TECHNOLOGY LETTERS, 1995, 7 (04) :360-362

[5]

Hillis WD, 1985, CONNECTION MACHINE

[6]

HORD RM, 1990, PARALLEL SUPERCOMPUT

[7]

HORD RM, 1982, ILLIAC 4 1 SUPERCOMP

[8] DIGITAL OPTICAL CELLULAR IMAGE-PROCESSOR (DOCIP) - EXPERIMENTAL IMPLEMENTATION [J].

HUANG, KS ;

SAWCHUK, AA ;

JENKINS, BK ;

CHAVEL, P ;

WANG, JM ;

WEBER, AG ;

WANG, CH ;

GLASER, I .

APPLIED OPTICS, 1993, 32 (02) :166-173

[9] BINARY IMAGE ALGEBRA AND OPTICAL CELLULAR LOGIC PROCESSOR DESIGN [J].

HUANG, KS ;

JENKINS, BK ;

SAWCHUK, AA .

COMPUTER VISION GRAPHICS AND IMAGE PROCESSING, 1989, 45 (03) :295-345

[10] PARALLEL ARCHITECTURES FOR DIGITAL OPTICAL CELLULAR IMAGE-PROCESSING [J].

HUANG, KS ;

KUZNIA, CB ;

JENKINS, BK ;

SAWCHUK, AA .

PROCEEDINGS OF THE IEEE, 1994, 82 (11) :1711-1723

← 1 2 3 4 →