A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications

被引：2

作者：

Somasekhar, D ^{[1
]}

Lu, SL ^{[1
]}

Bloechel, B ^{[1
]}

Dermer, G ^{[1
]}

Lai, K ^{[1
]}

Borkar, S ^{[1
]}

De, V ^{[1
]}

机构：

[1] Intel Labs, Microprocessor Res Labs, Hillsboro, OR USA

来源：

ESSCIRC 2005: PROCEEDINGS OF THE 31ST EUROPEAN SOLID-STATE CIRCUITS CONFERENCE | 2005年

关键词：

D O I：

10.1109/ESSCIR.2005.1541633

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 10Mb planar 1T-1C DRAM chip is implemented in an unmodified 150nm micro-processor logic process. It achieves 15GBytes/sec bandwidth, 9.5nsec read access time with 197mW power at 1.5V, 110 degrees C. Worst-case refresh period is 100 mu S at 110 degrees C with refresh power density of 0.18W/cm(2). Effective bit density of 42Mb/cm(2) is similar to 3X better than the best 6T SRAM cache in the same technology.

引用

页码：355 / 358

页数：4

共 6 条

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