Si, SiGe Nanowire Devices by Top-Down Technology and Their Applications

被引：126

作者：

Singh, Navab ^{[1
]}

Buddharaju, Kavitha D. ^{[1
]}

Manhas, S. K. ^{[2
]}

Agarwal, A. ^{[1
]}

Rustagi, Subhash C. ^{[1
]}

Lo, G. Q. ^{[1
]}

Balasubramanian, N. ^{[3
]}

Kwong, Dim-Lee ^{[1
]}

机构：

[1] Inst Microelect, Singapore 117685, Singapore

[2] Indian Inst Technol, Dept Elect & Comp Engn, Roorkee 247667, Uttar Pradesh, India

[3] Silterra, Kulim 09000, Malaysia

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2008年 / 55卷 / 11期

关键词：

Gate-all-around (GAA) nanowire (NW) transistors; Nonvolatile memory (NVM); NW CMOS; NW logic; top-down technology;

D O I：

10.1109/TED.2008.2005154

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Nanowire (NW) devices, particularly the gate-all-around (GAA) CMOS architecture, have emerged as the frontrunner for pushing CMOS scaling beyond the roadmap. These devices offer unique advantages over their planar counterparts which make them feasible as an option for 22-nm and beyond technology nodes. This paper reviews the current technology status for realizing the GAA NW device structures and their applications in logic circuit and nonvolatile memories. We also take a glimpse into applications of NWs in the "more-than-Moore" regime and briefly discuss the application of NWs as biochemical sensors. Finally, we summarize the status and outline the challenges and opportunities of the NW technology.

引用

页码：3107 / 3118

页数：12

共 74 条

[1] Strain-controlled growth of nanowires within thin-film cracks [J].

Adelung, R ;

Aktas, OC ;

Franc, J ;

Biswas, A ;

Kunz, R ;

Elbahri, M ;

Kanzow, J ;

Schürmann, U ;

Faupel, F .

NATURE MATERIALS, 2004, 3 (06) :375-379

[2] Silicon nanowire sensor array using top-down CMOS technology [J].

Agarwal, Ajay ;

Buddharaju, K. ;

Lao, I. K. ;

Singh, N. ;

Balasubramanian, N. ;

Kwong, D. L. .

SENSORS AND ACTUATORS A-PHYSICAL, 2008, 145 :207-213

[3] Strained n-MOSFET with embedded Source/Drain stressors and strain-transfer structure (STS) for enhanced transistor performance [J].

Ang, Kah-Wee ;

Lin, Jianqiang ;

Tung, Chih-Hang ;

Balasubramanian, Narayanan ;

Samudra, Ganesh S. ;

Yeo, Yee-Chia .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (03) :850-857

[4]

[Anonymous], 2006, Electron Devices Meeting

[5]

[Anonymous], 2006, IEDM, DOI [10.1109/IEDM.2006.346841, DOI 10.1109/IEDM.2006.346841]

[6] The high-k solution [J].

Bohr, Mark T. ;

Chau, Robert S. ;

Ghani, Tahir ;

Mistry, Kaizad .

IEEE SPECTRUM, 2007, 44 (10) :29-35

[7] Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach [J].

Buddharaju, K. D. ;

Singh, N. ;

Rustagi, S. C. ;

Teo, Selin H. G. ;

Lo, G. Q. ;

Balasubramanian, N. ;

Kwong, D. L. .

SOLID-STATE ELECTRONICS, 2008, 52 (09) :1312-1317

[8] Gate-All-Around Si-nanowire CMOS inverter logic fabricated using top-down approach [J].

Buddharaju, K. D. ;

Singh, N. ;

Rustagi, S. C. ;

Teo, Selin H. G. ;

Wong, L. Y. ;

Tang, L. J. ;

Tung, C. H. ;

Lo, G. Q. ;

Balasubramanian, N. ;

Kwong, D. L. .

ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2007, :303-306

[9] Quantitative real-time measurements of DNA hybridization with alkylated nonoxidized silicon nanowires in electrolyte solution [J].

Bunimovich, Yuri L. ;

Shin, Young Shik ;

Yeo, Woon-Seok ;

Amori, Michael ;

Kwong, Gabriel ;

Heath, James R. .

JOURNAL OF THE AMERICAN CHEMICAL SOCIETY, 2006, 128 (50) :16323-16331

[10] Extremely scaled silicon nano-CMOS devices [J].

Chang, LL ;

Choi, YK ;

Ha, DW ;

Ranade, P ;

Xiong, SY ;

Bokor, J ;

Hu, CM ;

King, TJ .

PROCEEDINGS OF THE IEEE, 2003, 91 (11) :1860-1873

← 1 2 3 4 5 6 7 8 →