Deep-submicron microprocessor design issues

被引:60
作者
Flynn, MJ [1 ]
Hung, P [1 ]
Rudd, KW [1 ]
机构
[1] Stanford Univ, Stanford Architecture & Arithmet Grp, Stanford, CA 94305 USA
关键词
D O I
10.1109/40.782563
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
TO FULLY EXPLOIT SHRINKING FEATURE SIZES AND AVOID BEING OVERWHELMED BY COMPLEXITY, MICROPROCESSOR DESIGNERS MUST KEEP UP WITH TECHNOLOGY TRENDS, UNDERSTAND SPECIFIC APPLICATIONS, AND USE ADVANCED CAD TOOLS.
引用
收藏
页码:11 / 22
页数:12
相关论文
共 22 条
[1]  
BAKOGLU HB, 1990, CIRCUIT INTERCONNECT
[2]  
BENNETT JE, 1998, THESIS STANFORD U
[3]   LOW-POWER CMOS DIGITAL DESIGN [J].
CHANDRAKASAN, AP ;
SHENG, S ;
BRODERSEN, RW .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (04) :473-484
[4]   Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects [J].
Chen, K ;
Hu, CM ;
Fang, P ;
Lin, MR ;
Wollesen, DL .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1997, 44 (11) :1951-1957
[5]  
Cotton L., 1969, AFIPS Spring Joint Computer Conference, P581
[6]  
DEMICHELI G, 1998, HARDWARE SOFTWARE CO
[7]   OPTIMAL PIPELINING [J].
DUBEY, PK ;
FLYNN, MJ .
JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 1990, 8 (01) :10-19
[8]  
Flynn M., 1995, Computer Architecture
[9]  
FU S, 1999, THESIS STANFORD U
[10]   CMOS DEVICE MODELING FOR SUBTHRESHOLD CIRCUITS [J].
GODFREY, MD .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, 1992, 39 (08) :532-539