Extending Dual Stress Liner Process to High Performance 32nm Node SOI CMOS Manufacturing

被引：4

作者：

Cai, M. ^{[1
]}

Greene, B. J. ^{[1
]}

Strane, J. ^{[1
]}

Belyansky, M. ^{[1
]}

Tamweber, F. ^{[1
]}

Lee, D. ^{[2
]}

van Meer, H. ^{[2
]}

Laffosse, E. ^{[3
]}

Luning, S. ^{[2
]}

Mocuta, D. ^{[1
]}

Maciejewski, E. ^{[1
]}

机构：

[1] IBM Semicond Res & Dev Ctr, IBM Syst & Technol Grp, Hopewell Jct, NY 12533 USA

[2] IBM Semicond Res & Dev Ctr, Adv Micro Devices, Hopewell Jct, NY 12533 USA

[3] IBM Semicond Res & Dev Ctr, Freescale Semicond, Hopewell Jct, NY 12533 USA

来源：

2008 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS | 2008年

关键词：

D O I：

10.1109/SOI.2008.4656273

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Dual stress liner process for high performance SOI CMOS technology at 32nm technology node is improved through the use of dep-etch-dep, etch back, and spacer removal techniques. The stress benefit of DSL is preserved with improved gap fill for the manufacturing of sub-32nm gate length transistors.

引用

页码：17 / +

页数：2

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