Dual stress liner for high performance sub-45nm gate length SOICMOS manufacturing

被引：148

作者：

Yang, HS ^{[1
]}

Malik, R ^{[1
]}

Narasimha, S ^{[1
]}

Li, Y ^{[1
]}

Divakaruni, R ^{[1
]}

Agnello, P ^{[1
]}

Allen, S ^{[1
]}

Antreasyan, A ^{[1
]}

Arnold, JC ^{[1
]}

Bandy, K ^{[1
]}

Belyansky, M ^{[1
]}

Bonnoit, A ^{[1
]}

Bronner, G ^{[1
]}

Chan, V ^{[1
]}

Chen, X ^{[1
]}

Chen, Z ^{[1
]}

Chidambarrao, D ^{[1
]}

Chou, A ^{[1
]}

Clark, W ^{[1
]}

Crowder, SW ^{[1
]}

Engel, B ^{[1
]}

Harifuchi, H ^{[1
]}

Huang, SF ^{[1
]}

Jagannathan, R ^{[1
]}

Jamin, FF ^{[1
]}

Kohyama, Y ^{[1
]}

Kuroda, H ^{[1
]}

Lai, CW ^{[1
]}

Lee, HK ^{[1
]}

Lee, WH ^{[1
]}

Lim, EH ^{[1
]}

Lai, W ^{[1
]}

Mallikarjunan, A ^{[1
]}

Matsumoto, K ^{[1
]}

McKnight, A ^{[1
]}

Nayak, J ^{[1
]}

Ng, HY ^{[1
]}

Panda, S ^{[1
]}

Rengarajar, R ^{[1
]}

Steigerwalt, M ^{[1
]}

Subbanna, S ^{[1
]}

Subramanian, K ^{[1
]}

Sudijono, J ^{[1
]}

Sudo, G ^{[1
]}

Sun, SP ^{[1
]}

Tessier, B ^{[1
]}

Toyoshima, Y ^{[1
]}

Tran, P ^{[1
]}

Wise, R ^{[1
]}

Wong, R ^{[1
]}

机构：

[1] IBM Syst & Technol Grp, Hopewell Jct, NY 12533 USA

来源：

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST | 2004年

关键词：

D O I：

10.1109/IEDM.2004.1419385

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For the first time, tensile and compressively stressed nitride contact liners have been simultaneously incorporated into a high performance CMOS flow. This dual stress liner (DSL) approach results in NFET/PFET effective drive current enhancement of 15%/32% and saturated drive current enhancement of 11%/20%. Significant hole mobility enhancement of 60% is achieved without using SiGe. Inverter ring oscillator delay is reduced by 24% with DSL. Overall yield for the DSL process is comparable to that of a similar technology without DSL. Single and multi-core SOI microprocessors are being manufactured using the DSL process in multiple, high-volume fabrication facilities.

引用

页码：1075 / 1077

页数：3

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