Effect of mechanical stress induced by etch-stop nitride: impact on deep-submicron transistor performance

被引：42

作者：

Ito, S ^{[1
]}

Namba, H ^{[1
]}

Hirata, T ^{[1
]}

Ando, K ^{[1
]}

Koyama, S ^{[1
]}

Ikezawa, N ^{[1
]}

Suzuki, T ^{[1
]}

Saitoh, T ^{[1
]}

Horiuchi, T ^{[1
]}

机构：

[1] NEC Corp Ltd, ULSI Device Dev Div, Adv CMOS Technol Grp, Kanagawa 2291198, Japan

来源：

MICROELECTRONICS RELIABILITY | 2002年 / 42卷 / 02期

关键词：

D O I：

10.1016/S0026-2714(01)00238-4

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper reports that process-induced mechanical stress affects the performance of short-channel MOSFETs, and focuses on the effect of a plasma-enhanced CVD nitride contact-etch-stop layer. The stress in the channel region induced by the nitride layer changes transconductance (G(m)), thereby changing the device performance. When the nitride stress varies from +300 MPa (tensile) to -1.4 GPa (compressive), NMOSFET performance degrades by up to 8% and PMOSFET performance improves up to 7%. These changes are caused by the modulation of the electron/hole mobilities, so controlling process-induced stress and considering this mobility change in a precise transistor model are necessary for deep-submicron transistor design. (C) 2002 Elsevier Science Ltd. All rights reserved.

引用

页码：201 / 209

页数：9

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