2 GHz 2 Mbit 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology

被引：66

作者：

Somasekhar, Dinesh ^{[1
]}

Ye, Yibin Dale ^{[1
]}

Aseron, Paolo ^{[1
]}

Lu, Shih-Lien ^{[1
]}

Khellah, Muhammad M. ^{[1
]}

Howard, Jason ^{[1
]}

Ruhl, Greg ^{[1
]}

Karnik, Tanay ^{[1
]}

Borkar, Shekhar ^{[1
]}

De, Vivek K. ^{[1
]}

Keshavarzi, Ali ^{[1
]}

机构：

[1] Intel Corp, Circuit Res Labs, Hillsboro, OR 97124 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2009年 / 44卷 / 01期

关键词：

Bandwidth; dram; eDRAM; gain cell; memory; 2T cell; 3T cell;

D O I：

10.1109/JSSC.2008.2007155

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present 2 Mb 2T PMOS gain cell macro on 65 nm logic process that has high bandwidth of 128 GBytes/sec, fast cycle time of 2 ns and 6-clock cycles access time at 2 GHz. Macro features a full-rate pipelined architecture, ground precharge bitline, non-destructive read-out, partial write support and 128-row refresh to tolerate short refresh time. Cell is 2X denser than SRAM and is voltage compatible with logic.

引用

页码：174 / 185

页数：12

共 10 条

[1] A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 μm2 SRAM cell [J].

Bai, P ;

Auth, C ;

Balakrishnan, S ;

Bost, M ;

Brain, R ;

Chikarmane, V ;

Heussner, R ;

Hussein, M ;

Hwang, J ;

Ingerly, D ;

James, R ;

Jeong, J ;

Kenyon, C ;

Lee, E ;

Lee, SH ;

Lindert, N ;

Liu, M ;

Ma, Z ;

Marieb, T ;

Murthy, A ;

Nagisetty, R ;

Natarajan, S ;

Neirynck, J ;

Ott, A ;

Parker, C ;

Sebastian, J ;

Shaheed, R ;

Sivakurnar, S ;

Steigerwald, J ;

Tyagi, S ;

Weber, C ;

Woolery, B ;

Yeoh, A ;

Zhang, K ;

Bohr, M .

IEEE INTERNATIONAL ELECTRON DEVICES MEETING 2004, TECHNICAL DIGEST, 2004, :657-660

[2]

BARTH J, 2007, ISSCC FEB, P486

[3]

BLALOCK TN, 1990, S VLSI CIRC JUL, P13

[4]

Ikeda N., 2002, S VLSI TECHN, P168

[5]

Itoh K, 2002, INT CONF MICROELECTR, P497, DOI 10.1109/MIEL.2002.1003306

[6]

REGITZ WM, 1970, IEEE INT SOL STAT CI, P42

[7]

Somasekhar D., 2002, ESSCIRC 2002. Proceedings of the 28th European Solid-State Circuit Conference, P127

[8] A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications [J].

Somasekhar, D ;

Lu, SL ;

Bloechel, B ;

Dermer, G ;

Lai, K ;

Borkar, S ;

De, V .

ESSCIRC 2005: PROCEEDINGS OF THE 31ST EUROPEAN SOLID-STATE CIRCUITS CONFERENCE, 2005, :355-358

[9]

Wang Y., 2007, IEEE INT SOLID STATE, P324

[10] A SRAM design on 65nm CMOS technology with integrated leakage reduction scheme [J].

Zhang, K ;

Bhattacharya, U ;

Chen, Z ;

Hamzaoglu, F ;

Murray, D ;

Vallepalli, N ;

Wang, Y ;

Zheng, B ;

Bohr, M .

2004 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS, 2004, :294-295

← 1 →