A survey of circuit innovations in ferroelectric random-access memories

This paper surveys circuit innovations in ferroelectric memories at three circuit levels: memory cell, sensing, and architecture. A ferroelectric memory cell consists of at least one ferroelectric capacitor; where binary data are stored, and one or two transistors that either allow. access to the capacitor or amplify its content for a read operation. Once a cell is accessed for a vend operation, its data are presented in the form of an analog signal to a sense amplifier, where it is compared against a reference voltage to determine its logic level. The circuit techniques used to generate the reference voltage must be robust to semiconductor processing variations across the chip and the device imperfections of ferroelectric capacitors. We review six methods of generating a reference voltage, two being presented for the first time in this paper These methods are discussed and evaluated in terms of their accuracy, area overhead and sensing complexity. Ferroelectric memory ies share architectural features such as addressing schemes and input/output circuitry with other types of random-access memories such as dynamic random-access memories. However they have distinct features with respect to accessing the stored data, sensing, and overall circuit topology. We review nine different architectures for ferroelectric memories and discuss them in terms of speed, density, and power consumption.