An integrated high resolution CMOS timing generator based on an array of delay locked loops

This paper describes the architecture and performance of a new high resolution timing generator used as a building block for time-to-digital converters (TDC) and clock alignment functions. The timing generator is implemented as an array of delay locked loops. This architecture enables a timing generator with subgate delay resolution to be implemented in a standard digital CMOS process. The TDC function is implemented by storing the state of the timing generator signals in an asynchronous pipeline buffer when a hit signal is asserted, The clock alignment function is obtained by selecting one of the timing generator signals as an output clock, The proposed timing generator has been mapped into a 1.0 mu m CMOS process and an rms error of the time taps of 48 ps has been measured with a bin size of 0.15 ns, Used as a TDC device, an rms error of 76 ps has been obtained. A short overview of the basic principles of major TDC and timing generator architectures is given to compare the merits of the proposed scheme to other alternatives.