THE USE OF STABILIZED CMOS DELAY-LINES FOR THE DIGITIZATION OF SHORT-TIME INTERVALS

被引：158

作者：

RAHKONEN, TE

KOSTAMOVAARA, JT

机构：

[1] Department of Electrical Engineering, University of Oulu, Linnanmaa

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1993年 / 28卷 / 08期

关键词：

D O I：

10.1109/4.231325

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper discusses the basic advantages and limitations of using integrated digital CMOS delay lines for the digitization of short time intervals. Accuracies of 6-7 b and single-shot resolutions from 0.1 to 10 ns are demonstrated to be realizable using fully integrated, tapped, and voltage-controlled CMOS delay lines as a time base for the measurement.

引用

收藏

页码：887 / 894

页数：8

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