Investigation of deep submicron single and double gate SOI MOSFETs in accumulation mode for enhanced performance

被引：21

作者：

Rauly, E ^{[1
]}

Iñiguez, B ^{[1
]}

Flandre, D ^{[1
]}

机构：

[1] Univ Catholique Louvain, Microelect Lab, B-1348 Louvain, Belgium

来源：

ELECTROCHEMICAL AND SOLID STATE LETTERS | 2001年 / 4卷 / 03期

关键词：

Computer simulation - Electric current measurement - Electric field effects - Gates (transistor) - MOSFET devices - Semiconductor doping - Threshold voltage - Transconductance - Two dimensional;

D O I：

10.1149/1.1347225

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 [应用化学];

摘要：

The behavior of single and double gate accumulation mode silicon-on-insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs) is thoroughly investigated. Accumulation mode devices present advantages over inversion mode transistors regarding transconductance, ease of fabrication, and parasitic effects. We have concluded, from experimental results and 2D simulations, that short channel effects such as DIBL and subthreshold swing degradation are substantially reduced in the volume accumulation regime, being even lower in thin-film double gate accumulation mode SOI MOSFETs than in inversion mode double gate SOI devices for adequate technological characteristics. The potential of thin-film accumulation mode SOI MOS transistors down to sub-0.1 mum technologies and up to 125 degrees C is demonstrated. (C) 2001 The Electrochemical Society.

引用

页码：G28 / G30

页数：3

共 10 条

[1]

BALESTRA F, 1998, SOLID STATE DEVICES, P575

[2]

A physics-based short-channel current-voltage model for buried-channel MOSFETs [J].

Chyau, CG ;

Jang, SL .

SOLID-STATE ELECTRONICS, 1999, 43 (07) :1177-1188

[3]

Ghani T., 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), P415, DOI 10.1109/IEDM.1999.824182

[4]

CMOS technology - Year 2010 and beyond [J].

Iwai, H .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (03) :357-366

[5]

Semiconductor thickness effects in the double-gate SOI MOSFET [J].

Majkusiak, B ;

Janik, T ;

Walczak, J .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1998, 45 (05) :1127-1134

[6]

On the subthreshold swing and short channel effects in single and double gate deep submicron SOI-MOSFETs [J].

Rauly, E ;

Potavin, O ;

Balestra, F ;

Raynaud, C .

SOLID-STATE ELECTRONICS, 1999, 43 (11) :2033-2037

[7]

RAYNAUD C, 1999, P 1999 INT SOI C, P86

[8]

*SEM IND ASS, 1997, NAT TECHN ROADM SEM

[9]

*SILV INT, 1999, ATL V 5 0 0

[10]

MEASUREMENT OF THRESHOLD VOLTAGES OF THIN-FILM ACCUMULATION-MODE PMOS SOI TRANSISTORS [J].

TERAO, A ;

FLANDRE, D ;

LORATAMAYO, E ;

VANDEWIELE, F .

IEEE ELECTRON DEVICE LETTERS, 1991, 12 (12) :682-684

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