共 24 条
[1]
[Anonymous], 1975, ELECT DEVICES M
[2]
A 7.9/5.5psec room/low temperature SOI CMOS
[J].
INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST,
1997,
:415-418
[3]
Bohr MT, 1995, INTERNATIONAL ELECTRON DEVICES MEETING, 1995 - IEDM TECHNICAL DIGEST, P241, DOI 10.1109/IEDM.1995.499187
[4]
Low resistance Ti or Co salicided raised source drain transistors for sub-0.13μm CMOS technologies
[J].
INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST,
1997,
:103-106
[5]
Sub-100nm gate length metal gate NMOS transistors fabricated by a replacement gate process
[J].
INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST,
1997,
:821-824
[8]
FIEGNA C, 1993, P S VLSI TECH, P33
[9]
A high performance 50nm PMOSFET using decaborane (B10H14) ion implantation and 2-step activation annealing process
[J].
INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST,
1997,
:471-474
[10]
Sub-10-ps gate delay by reducing the current crowding effect at an extension
[J].
INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST,
1997,
:239-242