A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications

被引：179

作者：

Takeda, K ^{[1
]}

Hagihara, Y

Aimoto, Y

Nomura, M

Nakazawa, Y

Ishii, T

Kobatake, H

机构：

[1] NEC Corp Ltd, Syst Devices Res Labs, Sagamihara, Kanagawa 2291198, Japan

[2] NEC Elect, Core Dev Div, Kawasaki, Kanagawa 2118668, Japan

[3] NEC Corp Ltd, R&D Support Ctr, Sagamihara, Kanagawa 2291198, Japan

[4] NEC Elect, Server Syst Div, Kawasaki, Kanagawa 2118668, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2006年 / 41卷 / 01期

关键词：

static random access memory (SRAM); SRAM scaling; static noise margin;

D O I：

10.1109/JSSC.2005.859030

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

To help overcome limits to the speed of conventional SRAMs, we have developed a read-static-noise-margin-free SRAM cell. It consists of seven transistors, several of which are low-Vth nMOS transistors used to achieve both low-VDD and high-speed operations. For the same speed, the area of our proposed SRAM is 23% smaller than that of a conventional SRAM. Further, we have fabricated a 64-kb SRAM macro using 90-nm CMOS technology and have obtained with it a minimum VDD of 440 mV and a 20-ns access time with a 0.5-V supply.

引用

页码：113 / 121

页数：9

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