Power minimization derived from architectural-usage of VLIW processors

This paper presents an empirical approach to inferring lour pourer code generation techniques for VLIW processors. Architectural usage variables are used to generate equations for power prediction which are in turn used to infer new code generation techniques for low power. Unlike previous techniques, the methodology empirically derives a power prediction equation and then. based upon the coefficients of the architectural-usage variables identities new VLIW code generation techniques for low power. The approach is illustrated using functional unit usage within a VLIW architecture and identifies a new operation rebinding technique for lour power which improved pourer dissipation zip to 18%. The approach is general and results are verified with real power measurements. This result is important for developing a general methodology for pourer minimization of embedded DSP software since low power is critical to complex DSP applications in many cost sensitive markets.