Behavioral modeling phase-locked loops for mixed-mode simulation

被引:12
作者
Antao, BAA [1 ]
ElTurky, FM [1 ]
Leonowich, RH [1 ]
机构
[1] AT&T BELL LABS,ALLENTOWN,PA 18103
关键词
phase-locked loops; behavioral modeling; mixed-mode simulation; modeling language description;
D O I
10.1007/BF00713978
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Phase-locked Loops(PLLs) are a class of feedback systems with wide range of applications. A PLL in its entirety can be viewed as a closed-loop servosystem, comprised of three major functional subsystems; 1) Phase detectors, 2) Loop filters and 3) Voltage/Current controlled oscillators. The overall characteristics of the phase-locked loop are dependent on the realization of individual subsystems which have mixed analog-digital implementations. In simulating a PLL, one has to deal with the mixed-signal nature of most implementations, as well as the problem of simulating the PLL over a large number of signal cycles. Long simulation run times plague the simulation of a PLL using a conventional simulator, sometimes making such simulation impractical. In the methodology described in this paper, these drawbacks are overcome by the use of behavioral models and a mixed-signal simulation platform. This paper presents a general mixed-mode behavioral simulation methodology and the derivation of behavioral simulation models for various kinds of PLLs. The top-down and bottom-up modeling paradigms are illustrated through the use of examples of actual PLL designs. The simulation models are generated for the AT&T Bell Laboratories mixed analog-digital simulator, ATTSIM.
引用
收藏
页码:45 / 65
页数:21
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